1. Field of the Invention
The present invention relates to a semiconductor integrated circuit in which a dynamic random access memory (DRAM), a central processing unit (CPU), and the like are mounted on a same semiconductor chip.
2. Description of the Prior Art
FIG. 4 is a diagram showing a configuration of a conventional semiconductor integrated circuit having a DRAM, a central processing unit (CPU), a bus controller, and the like mounted on a same semiconductor chip 101. In FIG. 4, the reference number 101 designates a semiconductor chip, 102 denotes a CPU mounted on the semiconductor chip 101, 103 indicates a dynamic random access memory (DRAM) mounted on the semiconductor chip 101, and 104 designates a bus controller mounted on the semiconductor chip 101. The bus controller 104 incorporates a control circuit to perform an access control and a refresh control to the DRAM 101. The reference number 105 designates an internal bus group through which the CPU 101, the DRAM 103, and the bus controller 104 are connected to each other.
Next, a description will now be given of the operation of the conventional semiconductor integrated circuit having the DRAM 103 and other devices.
For example, the CPU 102 performs an access control operation and a refresh control operation as control operations to the DRAM 103.
First, the access control operation and the refresh control operation in the conventional semiconductor integrated circuit having the DRAM 103 and other devices mounted on the same semiconductor chip 101 will be explained.
Access control
The DRAM 103 is accessed in accordance with a DRAM access request transferred from the CPU 102 to the DRAM 103. During the DRAM access operation, when the DRAM 103 has the function of a page mode, it is checked whether a page hit occurs or not. When the page hit occurs, the DRAM 103 is accessed in the page mode.
The operation of the page mode in the DRAM 103 will be explained in detail by using a simple configuration model of the DRAM 103 shown in FIG. 5. In FIG. 5, the reference numbers 0 to 15 designate memory cells.
When the DRAM 103 is accessed, first, a row address is inputted, after this, a column address is inputted to the DRAM 103. For example, when a data item stored in the memory cell 9 is read, a target address becomes a binary number "1001". When the DRAM 103 is accessed, firstly, the row address "10" of a binary number is given to the row address decoder 501. Thereby, the word line 2 is activated by the row address decoder 501. Data items of four bits of the memory cells 8 to 11 are read on the bit lines 0 to 3.
Next, when the column address "01" of a binary number is given to the column address decoder 502, the bit line 1 is activated (or selected) by the column address decoder 502. Thereby, the data item stored on the target memory cell 9 is read out through an data input/output terminal to outside.
Thus, the DRAM access operation requires the row address and the column address for the target memory cell. When a data item stored in a memory cell connected to the same word line of the memory cell that has previously been accessed, the DRAM access operation requires only a target column address, not requires the same word address. For example, when the data item stored in the memory cell 11 is read immediately following the data item stored in the memory cell 9 is read, it is possible to read the data item stored in the memory cell 11 only by giving the target column address "11" of a binary number to the column address decoder 502, because the data items stored in the memory cells 8 to 11 have been already read on the bit lines 0 to 3.
However, in order to achieve the above operation, the following functions (1) or (2) of the DRAM 103 is required:
(1) The function to keep the activation state of the word line 2 while the memory cell 9 to the memory cell 11 are accessed; or
(2) The function to latch the data items of 4 bits stored in the memory cells 8 to 11 selected by a same word line that have been read simultaneously when the memory cell 9 is accessed. In this case, when the memory cell 11 is accessed, the data item in the memory cell 11 is read from a latch circuit to store the data items of 4 bits.
This access operation is called to as "a page mode". In order to perform the page mode operation, it is required to check whether a word line to be currently accessed is equal to the word line that have previously been accessed. When both the current target word line and the previous target word line are same, it is possible to perform the page mode operation (hereinafter, referred to as "a page hit"). When both word lines are different to each other, it must be required to perform a normal access operation (hereinafter, referred to as "a normal access").
Refresh control
The refresh operation for the DRAM 103 is performed according to a refresh request generated at a predetermined constant time period based on a counter data item output from an internal counter (omitted from the drawing). Furthermore, it must be required to perform tests for the function of bus controller 104 and the DRAM 103.
Hereinafter, a description will be given of the tests of the bus controller 104 and the DRAM 103.
Tests for the function of bus control
The tests for the function of the bus control for the bus group 105 formed on the semiconductor chip 101 includes the test to check whether the bus controller 104 performs correctly when a collision among a plurality of bus-access requests occurs or when a collision between the bus access request and the refresh request occurs. It is sufficient to consider only a case in which the refresh request is repeatedly generated every a predetermined time interval. However, in the test of the function of the bus, it must be required to consider cases in which a collision between the refresh request and the bus access request causes and a collision between the bus access requests while the refresh request does not occur.
When the refresh request is generated at a constant time interval and it is not generated at an optional time interval, it becomes difficult to perform a timing matching between the refresh request and the bus access request or the execution of the test operation must be waited until the refresh request is generated. It thereby causes drawbacks that the period of a program development becomes long and the time of the test operation becomes long.
Test for DRAM
FIG. 6 is a diagram showing the configuration of a part of the DRAM 103. In FIG. 6, transistors T1 to T3 are connected between the bit line B and the word lines W1 to W3, respectively. Each of the transistors T1 to T3 is connected to each of the capacitors C1 to C3, respectively. There is a test called to as "a Read Disturb test" in the tests for the DRAM 103.
Object of the Read Disturb test
When the word line W2 designated by the solid line shown in FIG. 6 is frequently accessed (or selected), noises cause on the adjacent word lines W1 and W3 that are not selected. In this situation, the transistors T1 and T3 connected to the adjacent word lines W1 and W3 enter ON even if those transistors T1 and T3 are not selected. Then, electric charges in the capacitors C1 and C3 are discharged, so that the data item stored in the capacitors C1 and C3 are changed from 1 to zero, respectively. The Read Disturb test may detect the above error state.
The operation of the Read Disturb test will be explained with reference to FIG. 7.
First, as shown in the step ST1, initial data items are written into all bits as all memory cell in the DRAM 103. Next, as shown in the step ST2, the all bits designated by the row=0 are read out during a predetermined time period. In other words, the refresh operation is performed as shown in the step ST3 after the word line designated by the row address=0 is accessed repeatedly.
Then, as shown in the step ST4, the row address is incremented by 1 in order, and then the above steps ST2 and the step ST4 are performed repeatedly for the row addresses=0 to 3. After this operation, the all bits in the DRAM 103 are read out and then compared with the initial values.
Next, as shown in the step ST6, the all bits in the DRAM 103 are inverted, and then the above steps ST2 to ST5 are repeated.
Operation to be required for Read Disturb test
The operation at the step ST2 requires to perform the activation and the non-activation of the same word line. That is, the operation at the step ST2 requires to rise and to fall the voltage potential of the same word line, repeatedly. But, in the DRAM having the function of the page mode, the access operation to access the same word line that has previously been accessed enters the page hit, so that the word line is activated or not activated continuously.
The operation in the step ST2 must perform without the execution of the refresh operation. It is therefore required to perform the refresh operation at an optional timing.
During the test operation described above, interface terminals 103a to 103c in the DRAM 103 are electrically disconnected from the bus controller 104 and connected to the external terminals 106a to 106c in order to control the operation of the DRAM 103 by an external device (not shown) such as a memory tester instead of the bus controller 104. This is called to as "a memory test mode".
On the other hand, there are a burn-in test and a final test in the tests for the semiconductor integrated circuit (hereinafter also referred to as a large Scale integration (LSI)).
The burn-in test is the test in which an LSI is performed in a higher temperature and under a higher voltage in order to increase the occurrence of the initial failure and in order to decrease the shipping of the products involving the initial failure. The final test is performed after the burn-in test.
Because the tester to be used for the burn-in test has a lower timing accuracy and the number of test patterns is small and the kinds of tests are limited, this tester to be used in the burn-in test may test a plurality of LSI devices simultaneously and the cost of the tester is cheep. Therefore the cost of the burn-in test operation is low in general.
On the other hand, because the tester to be used for the final test operation has a higher accuracy and may test many kinds of test patterns, the cost of this tester becomes high. Therefore the cost of the final test becomes high.
The read disturb test requires the maximum time to keep the data items without any refresh operation during the operation for one word line shown in the step ST2. Because this time period is longer than the access time period of the DRAM 103, the read disturb test becomes longer than other DRAM tests. This causes to increase the testing cost of the DRAM. In general, the read disturb test is performed in the final test process. If it is performed in the burn-in test process, it is possible to decrease the testing cost of the DRAM.
However, because the tester to be used for the burn-in test has a small number of test patterns, the kinds of test programs are limited in use. That is, it must be required to execute the test program under the condition that the CUP 102 executes instructions in the test program automatically without inputting any test program through external pins of a semiconductor chip after the test program has been down-loaded into the semiconductor chip. Because the read disturb test requires an operation that is different from the normal operation described above, it must be required to input test patterns through the external pins of the semiconductor integrated circuit during the memory test mode. Because the read disturb test is not performed only by the execution of the CPU, the read disturb test and the burn-in test can not be performed simultaneously.
Since the conventional semiconductor integrated circuit having the DRAM and other devices mounted on the same semiconductor chip has the above configuration, it is difficult to generate and output a refresh request at optional time period and difficult to control the operation of the DRAM in the page mode. Thereby, the conventional semiconductor integrated circuit has drawbacks that the content of a test program becomes complicated and it causes to increase the testing time.
Furthermore, because test patterns are inputted through external terminals of the semiconductor integrated circuit during the memory test mode, it is difficult to perform the read disturb test during the burn-in test of a cheaper testing cost.